Evidence weight
High
2 primary source(s), 3 secondary source(s), 0 social source(s).
Map
BIS proposed rule (FR Doc. 2026-09872) published April 24, 2026, establishes specific performance floors for FPGA-based AI modules.
Published by Compute Statecraft. Read the method before treating an inferred claim as confirmed.
Evidence weight
High
2 primary source(s), 3 secondary source(s), 0 social source(s).
Last factual audit
May 3, 10:00 UTC
No explicit correction note is currently visible in the changelog.
Level 1
Directly supported by listed sources in the Confirmed section.
Level 2
Reasoned synthesis from multiple facts, made explicit in narrative provenance.
Level 3
What operators, firms, or regulators may do if the pattern holds.
Level 4
Signals that could change the assessment but are not yet proven outcomes.
BIS proposed rule (FR Doc. 2026-09872) published April 24, 2026, establishes specific performance floors for FPGA-based AI modules.
TSMC A16 (2nm) test yields reached 55% in May 2026, marking a critical milestone for backside power delivery geopolitics.
DeepSeek V4 Pro benchmarks (May 3, 2026) show leading efficiency in MoE architectures, driving SMIC 5nm demand.
The U.S. is shifting its chokepoint from training to actuation (edge FPGAs) that powers autonomous platforms.
Sign/Ship/Spend Decision (90-day): Industrial operators must built 75-day license latency into all A16/HBM4 procurement.
Binary Falsification Trigger: If SMIC 5nm yields drop below 15%, the 'Sovereign Efficiency' pivot stalls.
Kill-Switch: CCO; triggered by MATCH Act servicing window expiration (150 days).
Updated with TSMC A16 yield milestones and DeepSeek V4 Pro efficiency benchmarks.
Initial map release for Industrial FPGA thresholds and BIS attrition.
BIS proposed rule (FR Doc. 2026-09872) published April 24, 2026, establishes specific performance floors for FPGA-based AI modules.
TSMC A16 (2nm) test yields reached 55% in May 2026, marking a critical milestone for backside power delivery geopolitics.
DeepSeek V4 Pro benchmarks (May 3, 2026) show leading efficiency in MoE architectures, driving SMIC 5nm demand.
Deterministic performance (<5ms) and MoE efficiency become the primary capability metrics.
Backside power delivery (BSPDN) on A16 node is the next exclusive chokepoint for 2027.
HBM4 base-die integration commands a 30% premium in converged foundry-memory bids.
Canada's $2.4B program signals a shift toward NATO-aligned sovereign compute clusters.
Sign/Ship/Spend Decision (90-day): Industrial operators must built 75-day license latency into all A16/HBM4 procurement.
Binary Falsification Trigger: If SMIC 5nm yields drop below 15%, the 'Sovereign Efficiency' pivot stalls.
Kill-Switch: CCO; triggered by MATCH Act servicing window expiration (150 days).
federalregister.gov
Direct record that can confirm a claim if it matches the statement.
https://www.federalregister.gov/documents/2026/04/24/2026-09872/export-controls-on-fpga-based-ai-acceleration-modulesdigitimes.com
Interpretive or reported source that can support, contradict, or contextualize a claim.
https://digitimes.com/news/a20260503-tsmc-2nm-yieldsdeepseek.com
Interpretive or reported source that can support, contradict, or contextualize a claim.
https://deepseek.com/blog/v4-pro-benchmarksbloomberg.com
Interpretive or reported source that can support, contradict, or contextualize a claim.
https://www.bloomberg.com/news/articles/2026-04-10/trump-s-ai-chip-export-push-stymied-by-bureaucratic-bottleneckNo sources listed.